News of the day:Westmere, Sandy Bridge, Ive Bridge and Haswell - the future of processors Intel
July 25, 2008, 1:34 pm
Already the company Intel will soon introduce a new worldwide processor microarchitecture Nehalem, on the basis of which planned to produce a model family Core i7. Recall that the most notable innovation developers will be integrated controller RAM standard DDR3, which should increase productivity memory interface - the central processor, and thus significantly increase the productivity of the entire system. It Nehalem can be called the first stage to increase the complexity of integrated circuits CPU - until the case concerned only the memory controller, but then, in 2009, will be presented to mobile solutions with integrated graphics core. As for desktop microchips, it is still coming era of integrated video postponed, but in 2012, as we shall see, the developers of integrated circuits to equip additional coprocessor to enhance the effectiveness of devices when working with data in a vector format. In 2009, desktop microchips subjected to modification - the manufacture of integrated circuits will be translated into 32 - nm technology rails (kernel Westmere). Such a move should once again lower the cost of manufacturing processors, as well as reduce power consumption and allow increased frequency processors. In other words, only the expected finalization of the decisions, first used in architecture Nehalem, and the beginning of the release on the basis of that nucleus massive decisions, as well as a new generation of mobile chips. Next same serious architectural innovation is expected even a year later, when the audience greeted processors based on the kernel Sandy Bridge, and one of the most interesting solutions developers will work with microchips vector calculations - Advanced Vector Extensions. Here, developers aim to improve efficiency in the work of processors with multimedia data, graphics, etc. At the same time increasing overall productivity devices. The main features of a set of extensions are:work with vector data bit up to 256 bits - two-fold increase peak performance;execution of three to four calculations in a single instruction;improve the efficiency of the vector data. Based on Sandy Bridge leading global chipmeyker plans to release processors with the number up to eight cores, each will be equipped with 512 KB cache and own up to 16 MB cache distributed third level. Following the successful development of 32 - nm tehprotsessa and the start of construction on its basis processors Sandy Bridge company Intel will be forthcoming next generation of microchips - 22 - nm Ive Bridge. Release these devices is scheduled until the 2011 year and next year there will be solutions to the code Haswell, where developers are preparing major changes of the processor cache memory, yet unknown, but according to the promises of developers, revolutionary energy-saving technology, must also Ive Bridge coprocessor get to work with vector calculations. Of particular interest is the introduction of a new set of instructions - Fused Multiply Add (FMA). In this case, will be implemented immediately to work with four operands for one instruction to perform two operations at once, and the resignation of the multiplication/subtraction. The main advantages of FMA will include:increased density calculations, the increased accuracy of calculations and increased efficiency of working with vector and scalar data.