Some years ago, almost nobody but not well-known company Tilera presented at the annual Hot Chips conference its first product, immediately newcomer attention - 64 nuclear-power processor architecture Tile64 . This week the company announced two new chip - TilePro64 and TilePro36, representing the development of the ideas embodied in the debut processor. Instead of increasing the clock frequency and more subtle tehprotsessa - a common practice of evolution within the same chip architecture - Tilera went on the road complicating an already very unusual design.
Like its predecessor the new chips implemented in 90 nm rules. In TilePro, in addition to those already implemented in many Tile64 dedicated internal networks iMech, added another, for managing coherency cache memory, enabling productivity gains, in addition to the amount of cache memory for data and commands doubled - to 16 KB to the kernel. There are electronic circuit, selling household hash function and to distribute the data cache memory chip in order to avoid situations where a few kernels are working with the same contents of the cache. The new generation chip also contains a team specially added for working with audio and video, which is very important for streaming applications - one of the potential applications of the chip, as well as other teams to move and copy data in memory.
The built-in memory controller chips TilePro support the regime of alternation, similar to the arrays RAID0, which partly removes bottlenecks in data. At the cost of these improvements has been the increase in energy consumption by 5%, while productivity in Watts has almost doubled. In the real rate of increase in productivity applications TilePro64 on Tile64 of 1, 5 - 2, 5. If you compare TilePro64, working at 866 MHz with a 3 GHz quad Intel Xeon, the attitude of productivity watts would be 35 times in favor of the first, as compared with Texas Instruments DaVinci novelty of Tilera is 15 times better the significance of this figure.
TilePro64 has 64 core and 5, 6 MB distributed L2/L3 cache. To be published version with an operating frequency of 700 MHz and 866 users from 19 to 23 Watts. Urezannaya version, TilePro36, contains 36 nuclei and 3, 2 MB cache, frequency - 500 MHz, power consumption - W 10-16. Home TilePro64 sample shipments will begin next month, TilePro36 - near the end of the year. In the future plans of the company - the release of 120 nuclear-chip, which is expected to announce in late 2008 or early 2009,