Toshiba will introduce high-speed 128-bit memory FeRAM

 
February 10, 2009, 5:50 pm

   At the 2009 Conference ISSCC (International Solid-State Circuits Conference, an international conference on the latest developments in the fields of solid-state circuits and SOC-system (system-on-a -chip), the company will present a Toshiba high-speed 128 Mbit ferroelectric memory (FeRAM or FRAM) with a high-density packaging. The new chips, based on 130-nm technology, the unit cell area are 0, 252 microns. sq, recording speed-reading is 1 , 6 Gb/s, cycle time - 83 ns access time - 43 ns.
The new chips are built on FeRAM architecture ChainFeRAM, which, according to the manufacturer, provides scalability, and thus solve the problem inherent in a FeRAM, so and other varieties of nonvolatile memory, which they have so far been considered mainly as niche solutions. For example, FeRAM often known as a candidate to replace SRAM in embedded systems. The new development significantly increases the chances Toshiba FeRAM as a pretender to the status of a universal memory combines performance with energy independence DRAM memory. In addition to Toshiba, on the type of memory work as Fujitsu, Ramtron, Texas Instruments and others.
The new chips Toshiba broke its own record density of 32 Mbps and throughput of 200 Mbit/s by increasing the maximum value of transfer is eight times as compared with previous implementations FeRAM and overtaking other types of nonvolatile memory. According to the company, its 128-Mbit FeRAM chips represent currently the most advanced combination of performance and density of the layout of all development-volatile memory of any known types.
One of the major problems hindering the ability to increase chip FeRAM, it was reducing the level of the signal while reducing the size of the cells that maintain a value of polarization. To a large extent, to weaken the importance of this barrier has allowed the technology ChainFeRAM, providing in turn the work of a number of lines of data . Thus was able to reduce the number of navodok and to reduce the overall size of the chip. In addition, improved technology has allowed the registration to reduce parasitic capacity, and reach the level of the reader signal to 200 mV.

 

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• FeRAM replace SRAM 2009
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